Close

Presentation

Research Paper
:
Using High-Level Synthesis to Implement the Matrix-Vector Multiplication on FPGA
Event Type
Research Paper
Passes
Tags
HPC Accelerators
Parallel Algorithms
TimeTuesday, June 23rd8:30am - 9:00am
LocationAnalog 1, 2
DescriptionThis work presents how to implement the Matrix-Vector Multiplication (MVM) onto FPGA through the QuickPlay High-Level Synthesis flow. The motivations arise from the Adaptive Optics field, where the MVM is the core of the real-time control algorithm which controls the mirrors of a telescope to compensate for the effects of the atmospheric turbulence. The proposed implementation of the MVM exploits four different levels of parallelism: spatial and pipeline parallelism are used both at the fine (scalar instructions) and at the coarse (vector instructions) levels. To characterize the architecture being developed, a performance model has been developed and validated through the actual results obtained from runs on a prototype board based on the Intel ARRIA10 FPGA. Some details are given to describe how the algorithm has been implemented using the QuickPlay HLS flow. Performance results are presented, in terms of sustained computational speed and resources used in the hardware implementation.