Footprint-Aware Power Capping for Hybrid Memory Based Systems
TimeTuesday, June 23rd3:30pm - 3:55pm
DescriptionHigh Performance Computing (HPC) systems are facing severe limitations in both power and memory bandwidth/capacity. By now, these limitations have been addressed individually: to improve performance under a strict power constraint, power capping, which sets power limits to components/nodes/jobs, is an indispensable feature; for memory bandwidth/capacity increase, the industry has begun to support hybrid main memory designs that comprise multiple different technologies including emerging memories (e.g., 3D stacked DRAM or Non-Volatile RAM) in one compute node. However, few works look at the combination of both trends.
This paper explicitly targets power managements on hybrid memory based HPC systems and is based on the following observation: in spite of the system software’s efforts to optimize data allocations on such a system, the effective memory bandwidth can decrease considerably when we scale the problem size of applications. As a result, the performance bottleneck component changes in accordance with the footprint (or data) size, which then also changes the optimal power cap settings in a node. Motivated by this observation, we propose a power management concept called footprint-aware power capping (FPCAP) and a profile-driven software framework to realize it. Our experimental result on a real system using HPC benchmarks shows that our approach is successful in correctly setting power caps while keeping around 93/96% of performance/power-efficiency compared to the best settings.
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