Pattern-Aware Staging for Hybrid Memory Systems
Performance Analysis and Optimization
Programming Models & Languages
System Software & Runtime Systems
TimeTuesday, June 23rd1:45pm - 2:15pm
LocationAnalog 1, 2
DescriptionThe ever increasing demand for higher memory performance and—at the same time—larger memory capacity is leading the industry towards hybrid main memory designs, i.e., memory systems that consist of multiple different memory technologies. This is driven by the fact that no single memory technology is capable of providing both. This trend, however, naturally leads to one important question: how can we efficiently utilize such hybrid memories?
Our paper proposes a software-based approach to solve this challenge by deploying a pattern-aware staging technique. Our work is based on the following observations: (a) the high-bandwidth fast memory outperforms the large memory for memory intensive tasks; (b) but those tasks can run for much longer than a bulk data copy to/from the fast memory, especially when the access pattern is more irregular/sparse. We exploit these observations by applying the following staging technique if the accesses are irregular and sparse: (1) copying a chunk (few GB of sequential data) from large to fast memory; (2) performing a memory intensive task on the chunk; and (3) writing it back to the large memory. To check the regularity/sparseness of the accesses at runtime with negligible performance impact, we develop a lightweight pattern detection mechanism using a helper threading inspired approach with two different Bloom filters. Our case study using various scientific codes on a real system shows that our approach achieves significant speed-ups compared to executions with using only the large memory or hardware caching: 3x or 41% speedups in the best, respectively.