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Workshop
:
International Workshop on Machine Learning Hardware
Event Type
Workshop
Tags
Live Stream
Pre-Recorded
TimeThursday, June 25th6am - 11pm
LocationKontrast
DescriptionRecent years have seen a surge of investment in AI chip companies worldwide. These
companies are however mostly targeting applications outside of the scientific computing
community. As the use of ML accelerates in the HPC field itself, there is concern that the
scientific community should influence the design of this new specialized hardware. Indeed,
scientific computing has a distinctive set of requirements regarding workload type, usage
model, and platform administration. How those chips answer those demands will shape the
future of their integration within the global scientific computing infrastructure. In this
workshop, we propose to let the community and select vendors engage on questions related
to the programming models, compiler toolchains, system interfaces, and architecture
trade-offs of these chips. It is crucial that such interactions happen early in this field, and ISC
is a natural venue for those interactions to happen on a global scale. This proposal follows
the outcome of a successful SC19 BoF, where an emphasis on compiler technology
emerged. Accordingly, this workshop will feature an invited talk from A.Cohen (Google
Research) on the Multi-Level Intermediate Representation(MLIR) project, followed by
technical presentations from various industrial participants: Groq, SambaNova, GraphCore,
Cerebras, and Preferred Networks.
Workshop Organizers
Co-Director, Northestern / Argonne Inst. for Science and Eng.
Assistant Computer Scientist
WORKFLOWS AND DISTRIBUTED COMPUTING GROUP MANAGER
Team Leader, Processor Research Team