Compiler-assisted Correctness Checking and Performance Optimization for HPC
Event Type
TimeThursday, June 25th6am - 11pm
DescriptionPractical compiler-enabled programming environments, applied analysis methodologies, and end-to-end toolchains can contribute significantly to performance portability in the exascale era. The practical and applied use of compilation techniques, methods, and technologies, including static analysis and transformation, are imperative to improve the performance, correctness, and scalability of high-performance applications, middleware, and reusable libraries.
This workshop brings together a diverse group of researchers with a shared interest in applying compilation and source-to-source translation methodologies, among others, to enhance explicit parallel programming such as MPI, OpenMP, and hybrid models. These types of compiler technologies can also be applied to heterogeneous programming elements including FPGAs and GPUs in order to deliver higher achievable performance as compared to library-based methods and human-coded approaches taken in isolation.

Original papers will identify and solve challenges in the tradeoffs of scalability, performance, predictability, correctness, productivity, and portability on-node and at massive scale; strong-scaling, weak-scaling, and hybrid-scaling solutions assisted, augmented, and/or enabled by compiler technology are in scope. Topics of interest include but are not limited to: correctness checking of parallel programs, source-to-source translation of legacy MPI codes to improve performance-portability, instrumentation, and massively multipass FPGA compiler optimization strategies.